The present invention relates to semiconductor design technology, and more particularly, to an internal voltage generator for use in a semiconductor memory device and a method for operating the same.
Recently, it has been an issue to increase a storing quantity and an operational speed of a semiconductor memory device. However, in addition to these matters, it is also important to develop a low power semiconductor memory device with stable operation while running at a low power condition. Particularly for use in a portable system, e.g., a cellular phone and a laptop computer, a semiconductor memory device is required to consume less power.
One method of reducing power consumption is minimizing a current consumption of a core region included in a semiconductor memory device. The core region including a memory cell, a bit line and a word line is designed according to an extremely fine design-rule. Therefore, each memory cell has a very small size and consumes little power.
Particularly, a bit line precharge operation is an important technology for improving an operational speed of accessing a cell data. In a bit line precharge operation, a bit line is precharged to a predetermined voltage level before a data access so that the data access can be performed at high speed.
Under this condition, a memory cell has a mesh form where a plurality of word lines and a plurality of bit lines cross each other. Due to this structure, gate residue is generated because of a problem in a manufacturing process of a word line and a bit line. Due to the gate residue, a bridge phenomenon occurs. Such a bridge acts as a resistive short of a word line and a bit line.
FIG. 1 is a diagram showing a resistive short of a word line and a bit line.
As shown, a resistive short is generated due to the bridge phenomenon between a word line WL and a bit line pair BL and BLB. Under this condition, a leakage path is generated, i.e., a precharge voltage VBLP used for precharging the bit line pair BL and BLB at a standby state leaks to a ground of a word line driver 103 through the resistive short.
The above problem in a manufacturing process increases a power consumption of a semiconductor memory device and, thus, power efficiency is decreased and a performance of a product is degraded. For solving this problem, a bleeder circuit is provided.
FIG. 2 is a block diagram depicting a conventional bleeder circuit.
A bleeder circuit 203 is a bleeder transistor placed in a crossing between a word line array and a bit line sense amplifier array. Herein, a power supply voltage VEXTI is always biased to a gate of the bleeder transistor and the precharge voltage VBLP is supplied to a bit line precharge unit 201.
The bleeder circuit 203 is provided not in order to directly connect the precharge voltage VBLP to the bit line precharge unit 201, but to connect the precharge voltage VBLP to the bit line precharge unit 201 through the bleeder transistor so that a current flow is reduced by increased resistance.
Meanwhile, a bleed voltage VBLEED generated by the bleeder circuit 203 is transferred to the bit line precharge unit 201 through a particular wire. This is an option, i.e., if there is not the resistive short between the bit line and the word line, the general precharge voltage VBLP is supplied to the bit line precharge unit 201; otherwise, the bleed voltage VBLEED is supplied to the bit line precharge unit 201.
Therefore, there are different wires for transferring the precharge voltage VBLP and the bleed voltage VBLEED.
In this conventional circuit, even if the resistive short is not generated and, thus, the bleed voltage is not needed, the bleeder circuit 203 and the wire used for the bleed circuit 203 cannot be removed. Therefore, a size of a semiconductor memory device is increased.
Further, since a resistance due to the bridge between the word line and the bit line has a variable value, a amount of leakage current is variable. Accordingly, since only one fixed transistor is used for driving the precharge voltage VBLP, the conventional bleeder circuit has difficulty in corresponding to the various amount of a leakage current